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module m_sequences(clk,signal);
input clk;
output signal;
reg signal;
reg c1,c2,c3;
reg c0=1;
always@(posedge clk)
begin
c3<=c2;
c2<=c1;
c1<=c0;
c0<=c3 + c2 ;
signal<=c3;
end
endmodule
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