在quartus2中用vhdl编程出错，程序如下，希望各位大侠给予帮助

Question

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY vga IS
PORT(CLK,MD: IN STD_LOGIC;
HS,VS,R,G,B: OUT STD_LOGIC);
END vga;
ARCHITECTURE behav OF vga IS
SIGNAL CCH,CCV,CLKH,CLKV,HN,VN: INTEGER RANGE 0 TO 1000;
SIGNAL COH,COV: STD_LOGIC;
SIGNAL MMD: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL GRB: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(MD)
BEGIN
IF MD'EVENT AND MD='0' THEN
IF MMD="10" THEN MMD<="00";
ELSE MMD<=MMD+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CLKH=799 THEN CLKH<=0,COH<='1';
ELSE CLKH<=CLKH+1,COH<='0';
END IF;
IF CCH=639 THEN CCH<=0;
ELSE CCH<=CCH+1;
END IF;
END IF;
END PROCESS;
PROCESS(COH)
BEGIN
IF COH'EVENT AND COH='1' THEN
IF CLKV=524 THEN CLKV<=0,COV<='1';
ELSE CLKV<=CLKV+1,COV<='0';
END IF;
IF CCV=479 THEN CCV<=0;
ELSE CCV<=CCV+1;
END IF;
END IF;
END PROCESS;
PROCESS(MMD)
BEGIN
IF MMD="00" THEN
IF CCV<60 THEN GRB<="111",HN<='1';
ELSIF CCV<120 THEN GRB<="111",HN<=2;
ELSIF CCV<180 THEN GRB<="110",HN<=3;
ELSIF CCV<240 THEN GRB<="101",HN<=4;
ELSIF CCV<300 THEN GRB<="100",HN<=5;
ELSIF CCV<360 THEN GRB<="011",HN<=6;
ELSIF CCV<420 THEN GRB<="001",HN<=7;
ELSE GRB<="000",HN<=8;
END IF;
ELSIF MMD="01" THEN
IF CCH<80 THEN GRB<="111",VN<=1;
ELSIF CCH<160 THEN GRB<="111",VN<=2;
ELSIF CCH<240 THEN GRB<="110",VN<=3;
ELSIF CCH<320 THEN GRB<="101",VN<=4;
ELSIF CCH<400 THEN GRB<="100",VN<=5;
ELSIF CCH<480 THEN GRB<="011",VN<=6;
ELSIF CCH<560 THEN GRB<="001",VN<=7;
ELSE GRB<="000",VN<=8;
END IF;
ELSIF MMD="10" THEN
HN<=HN+VN;
VN<=HN%2;
IF VN=0 THEN GRB<="000";
ELSE GRB<="111";
END IF;
ELSE GRB<="000";
END IF;
END PROCESS;
HS<=COH;
VS<=COV;
G<=GRB(2);
R<=GRB(1);
B<=GRB(0);
END behav;

错误是第27行，can't determine definition of operator "<=" -- found 0 possible defitions

Answer 1

一下是我改的程序，我编译过了，没有错误！
提两点：1、在VHDL中好像没有"%"这个操作符，假如你要取模的话，可以用"mod”，取余的话"rem"。2、在两个语句之间是用的分号。例如：THEN GRB<="001",VN<=7; 应改为THEN GRB<="001";VN<=7;
假如有什么问题，请及时交流！
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY vga IS
PORT(
CLK,MD: IN STD_LOGIC;
HS,VS,R,G,B: OUT STD_LOGIC);
END vga;

ARCHITECTURE behav OF vga IS
SIGNAL CCH,CCV,CLKH,CLKV,HN,VN: INTEGER RANGE 0 TO 1000;
SIGNAL COH,COV: STD_LOGIC;
SIGNAL MMD: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL GRB: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(MD)
BEGIN
IF MD'EVENT AND MD='0' THEN
IF MMD="10" THEN MMD<="00";
ELSE MMD<=MMD+1;
END IF;
END IF;
END PROCESS;

PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CLKH=799 THEN CLKH<=0;COH<='1';
ELSE CLKH<=CLKH+1;COH<='0';
END IF;
IF CCH=639 THEN CCH<=0;
ELSE CCH<=CCH+1;
END IF;
END IF;
END PROCESS;

PROCESS(COH)
BEGIN
IF COH'EVENT AND COH='1' THEN
IF CLKV=524 THEN CLKV<=0;COV<='1';
ELSE CLKV<=CLKV+1;COV<='0';
END IF;
IF CCV=479 THEN CCV<=0;
ELSE CCV<=CCV+1;
END IF;
END IF;
END PROCESS;

PROCESS(MMD)
BEGIN
IF MMD="00" THEN
IF CCV<60 THEN GRB<="111";HN<=1;
ELSIF CCV<120 THEN GRB<="111";HN<=2;
ELSIF CCV<180 THEN GRB<="110";HN<=3;
ELSIF CCV<240 THEN GRB<="101";HN<=4;
ELSIF CCV<300 THEN GRB<="100";HN<=5;
ELSIF CCV<360 THEN GRB<="011";HN<=6;
ELSIF CCV<420 THEN GRB<="001";HN<=7;
ELSE GRB<="000";HN<=8;
END IF;
ELSIF MMD="01" THEN
IF CCH<80 THEN GRB<="111";VN<=1;
ELSIF CCH<160 THEN GRB<="111";VN<=2;
ELSIF CCH<240 THEN GRB<="110";VN<=3;
ELSIF CCH<320 THEN GRB<="101";VN<=4;
ELSIF CCH<400 THEN GRB<="100";VN<=5;
ELSIF CCH<480 THEN GRB<="011";VN<=6;
ELSIF CCH<560 THEN GRB<="001";VN<=7;
ELSE GRB<="000";VN<=8;
END IF;
ELSIF MMD="10" THEN
HN<=HN+VN;
VN<=HN mod 2;
IF VN=0 THEN GRB<="000";
ELSE GRB<="111";
END IF;
ELSE GRB<="000";
END IF;
END PROCESS;
HS<=COH;
VS<=COV;
G<=GRB(2);
R<=GRB(1);
B<=GRB(0);
END behav;