VHDL 错误near text "process"; expecting "if" 很急在线等

Question

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity s20122212 is
port(
input: in std_logic_vector(15 downto 0);
output_38: out std_logic_vector(7 downto 0);
output_pin: out std_logic_vector(7 downto 0);
clk: in std_logic);
end s20122212;

architecture arch of s20122212 is
begin
process(clk,input)
variable temp: std_logic_vector(3 downto 0);
variable count: integer;
begin
count<=0;
if clk'event and clk='1' then
if(count=0) then temp:=input(3 downto 0);
else if(count=1) then temp:=input(7 downto 4);
else if(count=2) then temp:=input(11 downto 8);
else if(count=3) then temp:=input(15 downto 12);
end if;

case temp(3 downto 0) is
when "0001" => output_pin<= "11111001";
when "0010" => output_pin<= "10100100";
when "0011" => output_pin<= "10110000";
when "0100" => output_pin<= "10011001";
when "0101" => output_pin<= "10010010";
when "0110" => output_pin<= "10000010";
when "0111" => output_pin<= "11111000";
when "1000" => output_pin<= "10000000";
when "1001" => output_pin<= "10010000";
when "1010" => output_pin<= "10001000";
when "1011" => output_pin<= "10000011";
when "1100" => output_pin<= "10100110";
when "1101" => output_pin<= "10100001";
when "1110" => output_pin<= "10000110";
when "1111" => output_pin<= "10001110";
end case;

if(count=0) then output_38<="00000001";
else if(count=1) then output_38<="00000010";
else if(count=2) then output_38<="00000100";
else if(count=3) then output_38<="00001000";
end if;

count<=count+1;
if(count=4) then count<=0;
end if;
end if;
end process;
end arch;

Answer 1

你的count运用有误。如果将count声明为变量，则变量的赋值要用":="，而不是"<="。
但从你的描述上看，不应当将其声明为变量，而应当将其声明为信号，也就是说，将variable count: integer;改成signal count: integer range 0 to 3;，并将这一句放在architecture arch of s20122212 is下面。
再将count<=count+1; if(count=4) then count<=0; end if; 改成
if (count=3) then count<=0; else count<=count+1; end if;
另外，去掉结构体最开始的count<=0;，应当就可以了。追问

我刚学vhdl几种复制都搞不清楚……count我是想用作一个计数的变量，这里用信号比较好吗？

追答

根据你的描述来看，应当将count声明为信号。

追问

呃，我按你说的改了，可是还是报了一样的错误说我少了一个end if……

追答

你的elsif语句错了，VHDL不是C，将你的
if(count=0) then output_38<="00000001";
else if(count=1) then output_38<="00000010";
else if(count=2) then output_38<="00000100";
else if(count=3) then output_38<="00001000";
end if;
中的所有else if改成elsif