使用Verilog HDL实现50MHz分频为20MHz

Question

使用Verilog HDL实现50MHz分频为20MHz

Answer 1

以下代码可以实现40%占空比的分频，供参考。

//clk_50m, clk_20m, rst
//cnt;
reg [2:0] cnt;

always@(posedge clk_50m)
if(!rst)
cnt <= 3'b0;
else if (cnt >= 4'h4)
cnt <= 3'b0;
else
cnt <= cnt + 1'b1;

always@(posedge clk_50m)
if(!rst)
clk_20m <= 1'b0;
else if (cnt == 3'h1)
clk_20m <= 1'b1;
else if (cnt == 3'h4)
clk_20m <= 1'b0;