用vhdl语言设计电路，完成一个序列信号发生器,用以产生序列信号101110110001。 求助啊

Question

好吧。我考试结束了。。。还是选你当最佳吧 没问题吧？

Answer 1

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity xlgen is
port(
clk : in STD_LOGIC;
res : in STD_LOGIC;
Q : out STD_LOGIC
);
end xlgen;
architecture rtl of xlgen is
signal temp : std_logic_vector (11 downto 0) ;
begin
process ( res, clk)
begin
if ( res= '1') then
temp <= "101110110001";
elsif ( clk'event and clk= '1') then
temp <= temp( 10 downto 0) & temp(11);
end if;
Q <= temp(0);
end process;
end rtl;本回答被提问者采纳